In an a.c. all points addressable plasma display panel (ACPDP), parallel conductor arrays disposed on glass plates with the conductor arrays disposed in a substantially orthogonal relationship are overcoated with a dielectric and refractory layer, and the glass plates edge sealed to form a panel, the panel containing an ionizable gas, the intersections of the conductor arrays defining display cells. The plasma display operates in three modes; write, sustain and erase. Writing is accomplished by applying appropriate amplitude drive signals to the conductor arrays whereby the display cells are selectively discharged to provide a visible display. The plasma discharge also forms a wall charge potential on selected cells which constitutes a memory. The display is maintained by a lower amplitude sustain signal which combines with the wall charge potential to continuously discharge selected display cells at a nominal 40 kHz rate. Erasing is performed by effectively neutralizing the wall charge at the selected cells, such that the combined wall charge potential and the sustain signal is insufficient to discharge the cell. The above described operation is more fully described in the referenced U.S. Pat. No. 4,591,847.
The waveform for sustain, write and erase operations serve separate functions as described above, and each function heretofore occupied separate time periods. The selection system full-selects part of the pels (picture elements) in the panel, half-selects others and non-selects the remaining pels. The signal summation is sustain plus write voltages for a full select, sustain voltage only for a half-select and sustain voltage minus write voltage for a non-select. The non-select case requires an adequate sustain voltage duration before the beginning of the write pulse to provide the non-sustain function.
In the aforereferenced U.S. Pat. No. 4,611,203, hereinafter designated the 203 patent, a 720.times.350 pel section of a 960.times.768 pel a.c. plasma panel operating from an IBM Personal Computer's CRT video adapter card was described. The video data rate was approximately 16 mHz, and the refresh rate was a non-interlaced 50 frames per second. Plasma panel technology is designed to operate at a nominal (.+-.10%) video cycle rate of 40 kHz to provide normal display intensity. In U.S. Pat. No. 4,611,203 patent, the system video updating was provided on a line by line basis by a full line write followed by a selective erase of the video data. To provide a nominal 40 mHz data rate needed for the 40 kHz cycle rate, it is apparent that the 16 mHz video data rate must be modified to approximate the update rate needed for plasma display operation.